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1 features ? high density, high performance electrically erasable complex programmable logic device C 64 macrocells C 5 product terms per macrocell, expandable up to 40 per macrocell C 44, 68, 84, 100 pins C 7 ns maximum pin-to-pin delay C registered operation up to 100 mhz C enhanced routing resources ? in-system programmability (isp) via jtag ? flexible logic macrocell C d/t/latch configurable flip flops C global and individual register control signals C global and individual output enable C programmable output slew rate C programmable output open collector option C maximum logic utilization by burying a register within a com output ? advanced power management features C automatic 100 m m m m a stand-by for z version C pin-controlled 4 ma stand-by mode (typical) C programmable pin-keeper inputs and i/os C reduced-power feature per macrocell ? available in commercial and industrial temperature ranges ? available in 44-, 68-, and 84-pin plcc; 44- and 100-pin tqfp; and 100-pin pqfp ? advanced ee technology C 100% tested C completely reprogrammable C 100 program/erase cycles C 20 year data retention C 2000v esd protection C 200 ma latch-up immunity ? jtag boundary-scan testing to ieee std. 1149.1-1990 and 1149.1a-1993 supported ? pci-compliant ? 3.3 or 5.0v i/o pins ? security fuse feature enhanced features ? improved connectivity (additional feedback routing, alternate input routing) ? output enable product terms ? d - latch mode ? combinatorial output with registered feedback within any macrocell ? three global clock pins ? itd (input transition detection) circuits on global clocks, inputs and i/o ? fast registered input from product term ? programmable pin-keeper option ? v cc power-up reset option ? pull-up option on jtag pins tms and tdi ? advanced power management features C edge controlled power down l C individual macrocell power option C disable itd on global clocks, inputs and i/o description the atf1504as is a high performance, high density complex programmable logic device (cpld) which utilizes atmels proven electrically erasable memory technology. with 64 logic macrocells and up to 68 inputs, it easily integrates logic from several high- performance ee cpld atf1504as atf1504asz rev. 0950dC07/98 (continued)
atf1504as(z) 2 44-lead plcc to p v i e w 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 tdi/i/o i/o i/o gnd pd1/i/o i/o i/o/tms i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 i/o i/o i/o i/o gnd vcc i/o pd2/i/o i/o i/o i/o i/o i/o i/o vcc gck2/oe2/i gclr/i oe1/i gck1/i gnd i/o/gclk3 i/o 68-lead plcc to p v i e w 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 i/o vcc i/o/td1 i/o i/o i/o gnd i/o/pd1 i/o i/o/tms i/o vcc i/o i/o i/o i/o gnd i/o i/o gnd i/o/tdo i/o i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o i/o i/o i/o 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 i/o i/o i/o i/o vcc i/o i/o gnd vcc i/o i/o/pd2 gnd i/o i/o i/o i/o vcc i/o i/o i/o gnd i/o i/o vcc i/oe2/gck2 gclr/i oe1/i i/gck1 gnd i/gck3 i/o vcc i/o/tck i/o 84-lead plcc to p v i e w 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 i/o vcc i/o/tdi i/o i/o i/o i/o gnd i/o/pd1 i/o i/o i/o/tms i/o i/o vcc i/o i/o i/o i/o i/o gnd i/o i/o gnd i/o/tdo i/o i/o i/o i/o vcc i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o i/o i/o 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 i/o i/o i/o i/o i/o vcc i/o i/o i/o gnd vcc i/o i/o i/o/pd2 gnd i/o i/o i/o i/o i/o vcc i/o i/o i/o i/o gnd i/o i/o i/o vcc i/oe2/gck2 i/gclr i/oe1 i/gck1 gnd i/gck3 i/o i/o vcc 1/o i/o i/o 44-lead tqfp to p v i e w 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 i/o/tdi i/o i/o gnd pd1/i/o i/o tms/i/o i/o vcc i/o i/o i/o i/o/tdo i/o i/o vcc i/o i/o i/o/tck i/o gnd i/o 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 i/o i/o i/o i/o gnd vcc i/o i/o/pd2 i/o i/o i/o i/o i/o i/o vcc i/oe2/gck2 gclr/i i/oe1 gck1/i gnd gck3 i/o
atf1504as(z) 3 100-lead pqfp to p v i e w 100-lead tqfp to p v i e w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc nc i/o i/o vccio i/o/tdi nc i/o nc i/o i/o i/o gnd i/o/pd1 i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o nc i/o nc i/o gnd nc nc nc nc i/o i/o gnd i/o/tdo nc i/o nc i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o nc i/o nc i/o vccio nc nc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o i/o/pd2 gnd i/o i/o i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o nc nc vccio i/o/tdi nc i/o nc i/o i/o i/o gnd i/o/pd1 i/o i/o i/o/tms i/o i/o vccio i/o i/o i/o nc i/o nc i/o i/o gnd i/o/tdo nc i/o nc i/o i/o i/o vccio i/o i/o i/o i/o/tck i/o i/o gnd i/o i/o i/o nc i/o nc i/o vccio gnd nc nc i/o i/o i/o i/o i/o vccio i/o i/o i/o gnd vccint i/o i/o i/o/pd2 gnd i/o i/o i/o i/o i/o nc nc i/o i/o i/o i/o i/o gnd i/o i/o i/o vccint input/oe2/gclk2 input/gclr input/oe1 input/gclk1 gnd i/o/gclk3 i/o i/o vccio i/o i/o i/o nc nc i/o 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
atf1504asz 4 ttl, ssi, msi, lsi and classic plds. the atf1504ass enhanced routing switch matrices increase usable gate count, and the odds of successful pin-locked design modifi- cations. the atf1504as has up to 68 bi-directional i/o pins and 4 dedicated input pins, depending on the type of device pack- age selected. each dedicated pin can also serve as a glo- bal control signal; register clock, register reset or output enable. each of these control signals can be selected for use individually within each macrocell. each of the 64 macrocells generates a buried feedback, which goes to the global bus. each input and i/o pin also feeds into the global bus. the switch matrix in each logic block then selects 40 individual signals from the global bus. each macrocell also generates a foldback logic term, which goes to a regional bus. cascade logic between macrocells in the atf1504as allows fast, efficient generation of com- plex logic functions. the atf1504as contains four such logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms. the atf1504as macrocell shown in figure 1, is flexible enough to support highly complex logic functions operating at high speed. the macrocell consists of five sections: product terms and product term select multiplexer; or/xor/cascade logic; a flip-flop; output select and enable; and logic array inputs. block diagram unused product terms are automatically disabled by the compiler to decrease power consumption. a security fuse, when programmed, protects the contents of the atf1504as. two bytes (16-bits) of user signature are accessible to the user for purposes such as storing project name, part number, revision or date. the user signature is accessible regardless of the state of the security fuse. the atf1504as device is an in-system programmable (isp) device. it uses the industry standard 4-pin jtag interface (ieee std. 1149.1), and is fully compliant with jtags boundary scan description language (bsdl). isp allows the device to be programmed without removing it from the printed circuit board. in addition to simplifying the manufacturing flow, isp also allows design modifications to be made in the field via software.
atf1504asz 5 product terms and select mux each atf1504as macrocell has five product terms. each product term receives as its inputs all signals from both the global bus and regional bus. the product term select multiplexer (ptmux) allocates the five product terms as needed to the macrocell logic gates and control signals. the ptmux programming is deter- mined by the design compiler, which selects the optimum macrocell configuration. or/xor/cascade logic the atf1504ass logic structure is designed to efficiently support all types of logic. within a single macrocell, all the product terms can be routed to the or gate, creating a 5- input and/or sum term. with the addition of the casin from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay. the macrocells xor gate allows efficient implementation of compare and arithmetic functions. one input to the xor comes from the or sum term. the other xor input can be a product term or a fixed high or low level. for combinato- rial outputs, the fixed level input allows polarity selection. for registered functions, the fixed levels allow demorgan minimization of product terms. the xor gate is also used to emulate t- and jk-type flip-flops. flip flop the atf1504ass flip flop has very flexible data and con- trol functions. the data input can come from either the xor gate, from a separate product term or directly from the i/o pin. selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (this feature is automatically implemented by the fitter software). in addition to d, t, jk and sr opera- tion, the flip flop can also be configured as a flow-through latch. in this mode, data passes through when the clock is high and is latched when the clock is low. the clock itself can either be one of the global clk signal gck[0 : 2] or an individual product term. the flip flop changes state on the clocks rising edge. when the gck signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. when the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. the flip flops asynchronous reset signal (ar) can be either the global clear (gclear), a product term, or always off. ar can also be a logic or of gclear with a product term. the asynchronous preset (ap) can be a product term or always off. output select and enable the atf1504as macrocell output can be selected as reg- istered or combinatorial. the buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered. the output enable multiplexer (moe) controls the output enable signals. any buffer can be permanently enabled for simple output operation. buffers can also be permanently disabled to allow use of the pin as an input. in this configu- ration all the macrocell resources are still available, includ- ing the buried feedback, expander and cascade logic. the output enable for each macrocell can be selected as either of the two dedicated oe input pins as an i/o pin con- figured as an input, or as an individual product term. global bus/switch matrix the global bus contains all input and i/o pin signals as well as the buried feedback signal from all 64 macrocells. the switch matrix in each logic block receives as its inputs all signals from the global bus. under software control, up to 40 of these signals can be selected as inputs to the logic block. foldback bus each macrocell also generates a foldback product term. this signal goes to the regional bus and is available to 4 macrocells. the foldback is an inverse polarity of one of the macrocells product terms. the 4 foldback terms in each region allows generation of high fan-in sum terms (up to 9 product terms) with a small additional delay.
atf1504asz 6 figure 1. atf1504as macrocell programmable pin-keeper option for inputs and i/os the atf1504as offers the option of programming all input and i/o pins so that pin keeper circuits can be utilized. when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. this circuitry prevents unused input and i/o lines from floating to intermediate voltage levels, which cause unnec- essary power consumption and system noise. the keeper circuits eliminate the need for external pull-up resistors and eliminate their dc power consumption. input diagram speed/power management the atf1504as has several built-in speed and power management features. the atf1504as contains circuitry that automatically puts the device into a low power stand- by mode when no logic transitions are occurring. this not only reduces power consumption during inactive periods, but also provides a proportional power savings for most applications running at system speeds below 50 mhz. this feature may be selected as a design option. i/o diagram to further reduce power, each atf1504as macrocell has a reduced power bit feature. this feature allows individual macrocells to be configured for maximum power savings. this feature may be selected as a design option. all atf1504ass also have an optional power down mode. in this mode, current drops to below 10 ma. when the power down option is selected, either pd1 or pd2 pins (or both) can be used to power down the part. the power down option is selected in the design source file. when enabled,
atf1504asz 7 the device goes into power down when either pd1 or pd2 is high. in the power down mode, all internal logic signals are latched and held, as are any enabled outputs. all pin transitions are ignored until the pd pin is brought low. when the power down feature is enabled, the pd1 or pd2 pin cannot be used as a logic input or output. how- ever, the pins macrocell may still be used to generate bur- ied foldback and cascade logic signals. all power-down ac characteristic parameters are com- puted from external input or i/o pins, with reduced power bit turned on. for macrocells in reduced-power mode (reduced power bit turned on), the reduced power adder, trpa, must be added to the ac parameters, which include the data paths t lad , t lac , t ic , t acl , t ach and t sexp . the atf1504as macrocell also has an option whereby the power can be reduced on a per macrocell basis. by enabling this power down option, macrocells that are not used in an application can be turned down thereby reduc- ing the overall power consumption of the device. each output also has individual slew rate control. this may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. outputs default to slow switching, and may be specified as fast switching in the design file. design software support atf1504as designs are supported by several third party tools. automated fitters allow logic synthesis using a variety of high level description languages and formats. power up reset the atf1504as has a power-up reset option at two differ- ent voltage trip levels when the device is being powered down. within the fitter, or during a conversion, if the power-reset option is turned on (which is the default option), the trip levels during power up or power down is at 2.8v. the user can change this default option from on to off (within the fitter or specify it as a switch during conver- sion). when this is done, the voltage trip level during power-down changes from 2.8v to 0.7v. this is to ensure a robust operating environment. the registers in the atf1504as are designed to reset dur- ing power up. at a point delayed slightly from v cc crossing vrst, all registers will be reset to the low state. the output state will depend on the polarity of the buffer. this feature is critical for state machine initialization. how- ever, due to the asynchronous nature of reset and the uncertainty of how v cc actually rises in the system, the fol- lowing conditions are required: 1. the v cc rise must be monotonic, 2. after reset occurs, all input and feedback setup times must be met before driving the clock pin- high, and, 3. the clock must remain stable during t d . security fuse usage a single fuse is provided to prevent unauthorized copying of the atf1504as fuse patterns. once programmed, fuse verify is inhibited. however, the 16-bit user signature remains accessible. programming atf1504as devices are in-system programmable (isp) devices utilizing the 4-pin jtag protocol. this capability eliminates package handling normally required for program and facilitates rapid design iterations and field changes. atmel provides isp hardware and software to allow pro- gramming of the atf1504as via the pc. isp is performed by using either a download cable, or a comparable board tester or a simple microprocessor interface. to facilitate isp programming by the automated test equipment (ate) vendors. serial vector format (svf) files can be created by atmel provided software utilities. atf1504as devices can also be programmed using stan- dard 3rd party programmers. with 3rd party programmer the jtag isp port can be disabled thereby allowing 4 addi- tional i/o pins to be used for logic. contact your local atmel representatives or atmel pld applications for details. isp programming protection the atf1504as has a special feature which locks the device and prevents the inputs and i/o from driving if the programming process is interrupted due to any reason. the inputs and i/o default to high-z state during such a condi- tion. in addition the pin keeper option preserves the former state during device programming. all atf1504as devices are initially shipped in the erased state thereby making them ready to use for isp. note: for more information refer to the designing for in-sys- tem programmability with atmel cplds application note.
atf1504asz 8 note: not more than one output at a time should be shorted. duration of short circuit test should not exceed 30 sec. note: typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. the ogi pin (high-voltage pin during programming) has a maximum capacitance of 12 pf. dc and ac operating conditions commercial industrial operating temperature (case) 0 c - 70 c-40 c - 85 c v ccint or v ccio (5v) power supply 5v 5% 5v 10% v ccio (3.3v) power supply 3.0v - 3.6v 3.0v - 3.6v dc characteristics symbol parameter condition min typ max units i il input or i/o low leakage current v in = v cc -2 -10 m a i ih input or i/o high leakage current 210 i oz tri-state output off-state current v o = v cc or gnd -40 40 m a i cc1 power supply current, stand-by v cc = max v in = 0, v cc std mode com. 120 ma ind. 150 ma z mode com. 100 m a ind. 100 m a i cc2 power supply current, power down mode v cc = max v in = 0, v cc pd mode 4 10 ma i os output short circuit current v out = 0.5v -150 ma v ccio supply voltage 5.0v device output com. 4.75 5.25 v ind. 4.5 5.5 v v ccio supply voltage 3.3v device output 3.0 3.6 v v il input low voltage -0.3 0.8 v v ih input high voltage 2.0 v ccint + 0.3 v v ol output low voltage v in = v ih or v il v ccio = min, i ol = 12 ma com. 0.45 v ind. v oh output high voltage v in = v ih or v il v ccio = min, i oh = -4.0 ma 2.4 v pin capacitance typ max units conditions c in 810 pf v in = 0v; f = 1.0 mhz c i/o 810 pf v out = 0v; f = 1.0 mhz
atf1504as(z) 9 absolute maximum ratings* temperature under bias.................................. -40c to +85c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may under- shoot to -2.0v for pulses of less than 20 ns. max- imum output pin voltage is v cc + 0.75v dc, which may overshoot to 7.0v for pulses of less than 20 ns. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) ac characteristics symbol parameter -7 -10 -15 -20 -25 units min max min max min max min max min max t pd1 input or feedback to non-registered output 7.5 10 3 15 20 25 ns t pd2 i/o input or feedback to non-registered feedback 793121625ns t su global clock setup time 6 7111620 ns t h global clock hold time 0 0000ns t fsu global clock setup time of fast input 3 3335ns t fh global clock hold time of fast input 0.5 0.5 1.0 1.5 2 mhz t cop global clock to output delay 4.5 5 8 10 13 ns t ch global clock high time 3 4567ns t cl global clock low time 3 4567ns t asu array clock setup time 3 3445ns t ah array clock hold time 2 3456ns t acop array clock output delay 7.510152025 ns t ach array clock high time 3 46 810ns t acl array clock low time 3 46 810ns t cnt minimum clock global period 810131722ns f cnt maximum internal global clock frequency 125 100 76.9 66 50 mhz t acnt minimum array clock period 810131722ns f acnt maximum internal array clock frequency 125 100 76.9 66 50 mhz (continued) = preliminary information
atf1504asz 10 note: see ordering information for valid part numbers. timing model ac characteristics (continued) symbol parameter -7 -10 -15 -20 -25 units min max min max min max min max min max f max maximum clock frequency 166.7 125 100 83.3 60 mhz t in input pad and buffer delay 0.5 0.5 2 2 2 ns t io i/o input pad and buffer delay 0.5 0.5 2 2 2 ns t fin fast input delay 112 22ns t sexp foldback term delay 4 5 8 10 12 ns t pexp cascade logic delay 0.8 0.8 1 1 1.2 ns t lad logic array delay 356 78ns t lac logic control delay 356 78ns t ioe internal output enable delay 223 34ns t od1 output buffer and pad delay (slow slew rate = off; v ccio = 5v; c l = 35 pf) 21.54 5 6ns t od2 output buffer and pad delay (slow slew rate = off; v ccio = 3.3v; c l = 35 pf) 2.5 2.0 5 6 7 ns t od3 output buffer and pad delay (slow slew rate = on; v ccio = 5v or 3.3v; c l = 35 pf) 55.58 1010ns (continued) = preliminary information
atf1504asz 11 notes: 1. see ordering information for valid part numbers. 2. the t rpa parameter must be added to the t lad , t lac ,t tic , t acl , and t sexp parameters for macrocells running in the reduced- power mode. ac characteristics (continued) symbol parameter -7 -10 -15 -20 -25 units min max min max min max min max min max t zx1 output buffer enable delay (slow slew rate = off; v ccio = 5.0v; c l = 35 pf) 4.0 5.0 7 9 10 ns t zx2 output buffer enable delay (slow slew rate = off; v ccio = 3.3v; c l = 35 pf) 4.5 5.5 7 9 10 ns t zx3 output buffer enable delay (slow slew rate = on; v ccio = 5.0v/3.3v; c l = 35 pf) 9 9 10 11 12 ns t xz output buffer disable delay (c l = 5 pf) 45678ns t su register setup time 3 3456 ns t h register hold time 2 3456 ns t fsu register setup time of fast input 3 3223 ns t fh register hold time of fast input 0.5 0.5 2 2 2.5 ns t rd register delay 12122ns t comb combinatorial delay 12122ns t ic array clock delay 35678ns t en register enable time 35678ns t glob global control delay 11111ns t pre register preset time 23456ns t clr register clear time 23456ns t uim switch matrix delay 11222ns t rpa reduced-power adder (2) 10 11 13 14 15 ns input test waveforms and measurement levels t r , t f = 1.5 ns typical output ac test loads note: *numbers in parenthesis refer to 3.0v operating condi- tions (preliminary). (3.0v)* (703 )* (8060 )* = preliminary information
atf1504asz 12 power down mode the atf1504as includes an optional pin controlled power down feature.when this mode is enabled, the pd pin acts as the power down pin. when the pd pin is high, the device supply current is reduced to less than 3 ma. during power down, all output data and internal logic states are latched and held. therefore, all registered and combinatorial output data remain valid. any outputs which were in a hi-z state at the onset will remain at hi-z. during power down, all input signals except the power down pin are blocked. input and i/o hold latches remain active to insure that pins do not float to indeterminate levels, further reducing system power. the power down pin feature is enabled in the logic design file. designs using the power down pin may not use the pd pin logic array input. however, all other pd pin mac- rocell resources may still be used, including the buried feedback and foldback product term array inputs. notes: 1. for slow slew outputs, add t sso . 2. pin or product term. jtag-bst/isp overview the jtag boundary-scan testing is controlled by the test access port (tap) controller in the atf1504as. the boundary-scan technique involves the inclusion of a shift- register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component bound- aries can be controlled and observed using scan testing principles. each input pin and i/o pin has its own boundary scan cell (bsc) in order to support boundary scan testing. the atf1504as does not currently include a test reset (trst) input pin because the tap controller is automati- cally reset at power up. the five jtag modes supported include: sample/preload, extest, bypass, idcode and highz. the atf1504ass isp can be fully described using jtags bsdl as described in ieee stan- dard 1149.1b. this allows atf1504as programming to be described and implemented using any one of the 3rd party development tools supporting this standard. the atf1504as has the option of using four jtag-stan- dard i/o pins for boundary scan testing (bst) and in-sys- tem programming (isp) purposes. the atf1504as is programmable through the four jtag pins using the ieee standard jtag programming protocol established by ieee standard 1149.1 using 5v ttl-level programming signals from the isp interface for in-system programming. the jtag feature is a programmable option. if jtag (bst or isp) is not needed, then the four jtag control pins are available as i/o pins. jtag boundary scan cell (bsc) testing the atf1504as contains up to 68 i/o pins and 4 input pins, depending on the device type and package type selected. each input pin and i/o pin has its own boundary scan cell (bsc) in order to support boundary scan testing as described in detail by ieee standard 1149.1. typical bsc consists of three capture registers or scan registers and up to two update registers. there are two types of bscs, one for input or i/o pin, and one for the macrocells. the bscs in the device are chained together through the capture registers. input to the capture register chain is fed in from the tdi pin while the output is directed to the tdo pin. capture registers are used to capture active device data signals, to shift data in and out of the device and to power down ac characteristics (1)(2) symbol parameter -7 -10 -15 -20 -25 units min max minmaxminmaxminmaxminmax t ivdh valid i, i/o before pd high 7 10 15 20 25 ns t gvdh valid oe (2) before pd high 7 10 15 20 25 ns t cvdh valid clock (2) before pd high 7 10 15 20 25 ns t dhix i, i/o dont care after pd high 12 15 25 30 35 ns t dhgx oe (2) dont care after pd high 12 15 25 30 35 ns t dhcx clock (2) dont care after pd high 12 15 25 30 35 ns t dliv pd low to valid i, i/o 11111 m s t dlgv pd low to valid oe (pin or term) 11111 m s t dlcv pd low to valid clock (pin or term) 11111 m s t dlov pd low to valid output 11111 m s = preliminary information
atf1504asz 13 load data into the update registers. control signals are gen- erated internally by the jtag tap controller. the bsc configuration for the input and i/o pins and macrocells are shown below. bsc configuration for input and i/o pins (except jtag tap pins) note: the atf1504as has pull-up option on tms and tdi pins. this feature is selected as a design option. bsc configuration for macrocell 0 1 dq 0 1 0 1 dq dq capture dr capture dr update dr 0 1 0 1 dq dq tdi tdi outj oej shift shift clock clock mode tdo tdo pin bsc macrocell bsc pin pin
atf1504asz 14 pci compliance the atf1504as also supports the growing need in the industry to support the new peripheral component inter- connect (pci) interface standard in pci-based designs and specifications. the pci interface calls for high current driv- ers which are much larger than the traditional ttl drivers. in general, plds and fpgas parallel outputs to support the high current load required by the pci interface. the atf1504as allows this without contributing to system noise while delivering low output to output skew. having a programmable high drive option is also possible without increasing output delay or pin capacitance. the pci electri- cal characteristics appear on the next page. pci voltage-to-current curves for +5v signaling in pull-up mode pci voltage-to-current curves for +5v signaling in pull-down mode 2.4 vcc 1.4 -2 -44 -178 current (ma) ac drive point dc drive point voltage pull up test point 2.2 vcc 0.55 3.6 95 380 current (ma) ac drive point dc drive point voltage pull down test point
atf1504as(z) 15 note: leakage current is with pin-keeper off. notes: 1. equation a: i oh = 11.9 (v out - 5.25) * (v out + 2.45) for v cc > v out > 3.1v. 2. equation b: i ol = 78.5 * v out * (4.4 - v out ) for 0v < v out < 0.71v. pci dc characteristics (preliminary) symbol parameter conditions min max units v cc supply voltage 4.75 5.25 v v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage -0.5 0.8 v i ih input high leakage current v in = 2.7v 70 m a i il input low leakage current v in = 0.5v -70 m a v oh output high voltage i out = -2 ma 2.4 v v ol output low voltage i out = 3 ma, 6 ma 0.55 v c in input pin capacitance 10 pf c clk clk pin capacitance 12 pf c idsel idsel pin capacitance 8 pf l pin pin inductance 20 nh pci ac characteristics (preliminary) symbol parameter conditions min max units i oh(ac) switching 0 < v out 1.4 -44 ma current high 1.4 < v out < 2.4 -44+(v out - 1.4)/0.024 ma 3.1 < v out < v cc equation a ma (test high) v out = 3.1v -142 m a i ol(ac) switching v out > 2.2v 95 ma current low 2.2 > v out > 0 v out /0.023 ma 0.1 > v out > 0 equation b ma (test point) v out = 0.71 206 ma i cl low clamp current -5 < v in -1 -25+(v in + 1)/0.015 ma slew r output rise slew rate 0.4v to 2.4v load 0.5 3 v/ns slew f output fall slew rate 2.4v to 0.4v load 0.5 3 v/ns
atf1504as(z) 16 oe (1, 2) global oe pins gclr global clear pin gclk (1, 2, 3) global clock pins pd (1, 2) power down pins tdi, tms, tck, tdo jtag pins used for boundary scan testing or in-system programming gnd ground pins v ccint v cc pins for the device (+5v - internal) v ccio v cc pins for output drivers (for i/o pins) (+5v or 3.3v - i/os) atf1504as dedicated pinouts dedicated pin 44-pin tqfp 44-pin j-lead 68-pin j-lead 84-pin j-lead 100-pin pqfp 100-pin tqfp input/oe2/gclk2 40 2 2 2 92 90 input/gclr 39 1 1 1 91 89 input/oe1 384468849088 input/gclk1374367838987 i/o /gclk3 35 41 65 81 87 85 i/o / pd (1,2) 5, 19 11, 25 17, 37 20, 46 14, 44 12, 42 i/o / tdi (jtag) 1 7 12 14 6 4 i/o / tms (jtag)7 1319231715 i/o / tck (jtag) 26 32 50 62 64 62 i/o / tdo (jtag) 32 38 57 71 75 73 gnd 4, 16, 24, 36 10, 22, 30, 42 6, 16, 26, 34, 38, 48, 58, 66 7, 19, 32, 42, 47, 59, 72, 82 13, 28, 40, 45, 61, 76, 88, 97 11, 26, 38, 43, 59, 74, 86, 95 v ccint 9, 17, 29, 41 3, 15, 23, 35 3, 35 3, 43 41, 93 39, 91 v ccio -- 11, 21, 31, 43, 53, 63 13, 26, 38, 53, 66, 78 5, 20, 36, 53, 68, 84 3, 18, 34, 51, 66, 82 n/c ---- 1, 2, 7, 9, 24, 26, 29, 30, 51, 52, 55, 57, 72, 74, 79, 80 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 # of signal pins 36 36 52 68 68 68 # user i/o pins 32 32 48 64 64 64
atf1504as(z) 17 atf1504as i/o pinouts mc plc 44-pin plcc 44-pin tqfp 68-pin plcc 84-pin plcc 100-pin pqfp 100-pin tqfp mc plc 44-pin plcc 44-pin tqfp 68-pin plcc 84-pin plcc 100-pin pqfp 100-pin tqfp 1 a 12 6 18 22 16 14 33 c 24 18 36 44 42 40 2 a - - - 21 15 13 34 c - - - 45 43 41 3 a/ pd1 115172014 1235 c/ pd2 25 19 37 46 44 42 4 a 9 3 15 18 12 10 36 c 26 20 39 48 46 44 5 a 8 2 14 17 11 9 37 c 27 21 40 49 47 45 6 a - - 13 16 10 8 38 c - - 41 50 48 46 7a---158 639c ---514947 8/ tdi a 7 1 12 14 6 4 40 c 28 22 42 52 50 48 9a - - 1012 4 2 41 c 29234454 54 52 10 a - - - 11 3 1 42 c - - - 55 56 54 11 a 6 44 9 10 100 98 43 c - - 45 56 58 56 12 a - - 8 9 99 97 44 c - - 46 57 59 57 13 a - - 7 8 98 96 45 c - - 47 58 60 58 14 a 5 43 5 6 96 94 46 c 31 25 49 60 62 60 15 a - - - 5 95 93 47 c - - - 61 63 61 16 a 4 42 4 4 94 92 48/ tck c 32265062 64 62 17 b 21 15 33 41 39 37 49 d 33 27 51 63 65 63 18 b - - - 40 38 36 50 d - - - 64 66 64 19 b 20 14 32 39 37 35 51 d 34 28 52 65 67 65 20 b 19 13 30 37 35 33 52 d 36 30 54 67 69 67 21 b 18 12 29 36 34 32 53 d 37 31 55 68 70 68 22 b - - 28 35 33 31 54 d - - 56 69 71 69 23 b - - - 34 32 30 55 d - - - 70 73 71 24b17112733 31 29 56/ tdo d 38325771 75 73 25 b 16 10 25 31 27 25 57 d 39 33 59 73 77 75 26 b - - - 30 25 22 58 d - - - 74 78 76 27 b - - 24 29 23 21 59 d - - 60 75 81 79 28 b - - 23 28 22 20 60 d - - 61 76 82 80 29 b - - 22 27 21 19 61 d - - 62 77 83 81 30 b 14 8 20 25 19 17 62 d 40 34 64 79 85 83 31 b - - - 24 18 16 63 d - - - 80 86 84 32/ tms b 13 7 19 23 17 15 64 d/ gclk3 41 35 65 81 87 85
atf1504as(z) 18 ordering information t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range 7.5 4.5 166.7 atf1504as-7 ac44 atf1504as-7 jc44 atf1504as-7 jc68 atf1504as-7 jc84 atf1504as-7 qc100 atf1504as-7 ac100 44a 44j 68j 84j 100q1 100a commercial (0 c to 70 c) 10 5 125 atf1504as-10 ac44 atf1504as-10 jc44 atf1504as-10 jc68 atf1504as-10 jc84 atf1504as-10 qc100 atf1504as-10 ac100 44a 44j 68j 84j 100q1 100a commercial (0 c to 70 c) 10 5 125 atf1504as-10 ai44 atf1504as-10 ji44 atf1504as-10 ji68 atf1504as-10 ji84 atf1504as-10 qi100 atf1504as-10 ai100 44a 44j 68j 84j 100q1 100a industrial (-40 c to +85 c) 15 8 100 atf1504as-15 ac44 atf1504as-15 jc44 atf1504as-15 jc68 atf1504as-15 jc84 atf1504as-15 qc100 atf1500as-15 ac100 44a 44j 68j 84j 100q1 100a commercial (0 c to 70 c) 15 8 100 atf1504as-15 ai44 atf1504as-15 ji44 atf1504as-15 ji68 atf1504as-15 ji84 atf1504as-15 qi100 atf1504as-15 ai100 44a 44j 68j 84j 100q1 100a industrial (-40 c to +85 c) package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier otp (plcc) 68j 68-lead, plastic j-leaded chip carrier (plcc) 84j 84-lead, plastic j-leaded chip carrier (plcc) 100q1 100-lead, plastic quad flat pack (pqfp) 100a 100-lead, thin quad flat pack (tqfp)
atf1504as(z) 19 20 12 83.3 atf1504asz-20 ac44 atf1504asz-20 jc44 atf1504asz-20 jc68 atf1504asz-20 jc84 atf1504asz-20 qc100 atf1504asz-20 ac100 44a 44j 68j 84j 100q1 100a commercial (0 c to 70 c) 25 15 70 atf1504asz-25 ac44 atf1504asz-25 jc84 atf1504asz-25 jc68 atf1504asz-25 jc84 atf1504asz-25 qc100 atf1504asz-25 ac100 44a 44j 68j 84j 100q1 100a commercial (0 c to 70 c) 25 15 70 atf1504asz-25 ai44 atf1504asz-25 ji84 atf1504asz-25 ji68 atf1504asz-25 ji84 atf1504asz-25 qi100 atf1504asz-25 ai100 44a 44j 68j 84j 100q1 100a industrial (-40 c to +85 c) ordering information (continued) t pd (ns) t co1 (ns) f max (mhz) ordering code package operation range package type 44a 44-lead, thin plastic gull wing quad flatpack (tqfp) 44j 44-lead, plastic j-leaded chip carrier otp (plcc) 68j 68-lead, plastic j-leaded chip carrier (plcc) 84j 84-lead, plastic j-leaded chip carrier (plcc) 100q1 100-lead, plastic quad flat pack (pqfp) 100a 100-lead, thin quad flat pack (tqfp)
atf1504as(z) 20 packaging information * controlling dimension: millimeters .045(1.14) x 45 pin no. 1 identify .045(1.14) x 30 - 45 .012(.305) .008(.203) .021(.533) .013(.330) .630(16.0) .590(15.0) .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .500(12.7) ref sq .032(.813) .026(.660) .050(1.27) typ .022(.559) x 45 max (3x) .656(16.7) .650(16.5) .695(17.7) .685(17.4) sq sq 44a , 44-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) dimensions in millimeters and (inches)* 44j , 44-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 ac 68j , 68-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 ae 84j , 84-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec standard ms-018 af
atf1504as(z) 21 packaging information *controlling dimension: millimeters pin 1 id 0.56(0.022) 0.44(0.018) 16.25(0.640) 15.75(0.620) 0.17(0.007) 0.27(0.011) 14.10(0.555) 13.90(0.547) 0.95(0.037) 1.27(0.05) 0.05(0.002) 0.15(0.006) 0.45(0.018) 0.75(0.030) 0-7 0.20(0.008) 0.10(0.004) pin 1 id .667(16.95) .687(17.44) .782(19.87) .792(20.12) .904(22.95) .923(23.45) 0.026(.65) bsc .009(0.22) .016(0.41) .134(3.40) max .004(0.10) min .028(0.73) .041(1.03) .546(13.87) .556(14.12) .004(0.10) .010(0.25) 0 7 100a, 100-lead, thin (1.0 mm) plastic gull wing quad flat package (tqfp) dimensions in millimeters and (inches)* 100q1 , 100-lead, plastic gull wing quad flat package (pqfp) dimensions in millimeters and (inches)

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